DigiTekXplorer - Building With AI

Five projects built in collaboration with AI, each one showing how the tools accelerate the design and implementation of real systems. They span Android app development, computer architecture, FPGA design, schematic capture, and hardware description languages. 

1. abDraw: Schematic Capture for Digital Designs

abDraw is a schematic capture tool for electrical block diagrams, written in Python. Symbols carry named pins that stay wired through every move, an orthogonal auto-router keeps connections readable as a sheet fills up, and buses, multi-sheet designs and netlist export take a drawing from sketch to documentation. PNG and PDF export produce figures usable in reports and on this site.

The tool exists because the commercial equivalents cost more than a retired engineer will spend, and drawing block diagrams by hand in a general-purpose drawing program loses the one thing that matters: the connections.

Tools: 

PyCharm 2025.1.1 

Claude

• AI Collaboration:  The hard part of a schematic editor is not drawing — it is the data model underneath, where a net has to survive every move, rename and re-route. I worked through that model with Claude before writing code, then had it generate the routing and hit-testing logic, which I integrated and corrected against real drawings. The auto-router took several rounds; the first versions produced routes that were technically correct and visually unreadable. 

2. abVisualRTL:  Visual FSM to HDL

abVisualRTL turns a drawn finite-state machine into synthesizable hardware. You place states, transitions and conditions on a canvas; the tool generates SystemVerilog or VHDL from the same diagram, with Moore and Mealy outputs, automatic state encoding, and a live HDL preview that updates as you draw.

State machines are where FPGA designs are won or lost, and the usual workflow — draw the diagram to think, then hand-translate it into HDL, then keep the two in step — wastes effort and invites mistakes. Here the diagram is the source.

Tools: 

PyCharm 2025.1.1 

Claude

• AI Collaboration:  I specified the generated HDL's structure — the coding style a synthesis tool will accept without complaint — and Claude wrote the generator against that specification. Verification stayed mine: generated code that looks right and synthesizes wrong is the failure mode here, so every example went through Vivado before I trusted the generator. 

3. B_Bot: BLE Android Control Application

I developed a custom Android application to wirelessly control the B-Bot rover via Bluetooth Low Energy (BLE). Using a combination of Android Studio and Google's Gemini Pro, I accelerated the development lifecycle.

Tools:

Android Studio 2024.3.1

Gemini

• AI Collaboration: Gemini was instrumental in generating the initial boilerplate code for Android's BLE services and characteristics. It also helped debug complex asynchronous callbacks and provided alternative implementations for the user interface layout in XML, allowing for rapid prototyping.

4. abCore16: Custom 16-bit Microprocessor and Ecosystem

The abCore16 project is a complete 16-bit microprocessor and its ecosystem. The microprocessor HDL was written in SystemVerilog.  The microprocessor's ecosystem was written entirely in Python. It features a custom CPU architecture and a comprehensive software development toolchain built within a PyCharm environment.

The ecosystem enables software development for the abCore16 CPU through two distinct compilation paths:

1. A simple, direct-to-assembly language.
2. A more powerful, C-like high-level language (SSL). This language supports modern programming constructs including functions with local variables, if/else, for, and while loops, and global one-dimensional arrays.

The toolchain provides a seamless workflow from high-level code to execution:

• A PLY-based C-like Compiler parses the source, builds an Abstract Syntax Tree (AST), and generates assembly code.
• An Assembler converts the assembly code into 16-bit binary machine code.
• A Simulator executes the binary code on a detailed model of the abCore16 CPU, providing cycle-by-cycle logging and state inspection.
• A Disassembler can reverse-engineer the binary back into human-readable assembly for verification and debugging.

The project serves as a practical, hands-on platform for exploring and implementing concepts in computer architecture and compiler design.

Tools:

PyCharm 2025.1.1

Gemini, ChatGPT

• AI Collaboration: This project was a deep partnership with Gemini to develop the Python code for the ecosystem and SystemVerilog HDL for the microprocessor.  ChatGPT was used to review the SystemVerilog code. Gemini was used as an architectural consultant to define the instruction set and addressing modes. The AI then generated foundational Python code for the assembler and the CPU's fetch-decode-execute cycle in the simulator, which I then integrated and refined.

5. abUART: FPGA-Based UART and Testbench in SystemVerilog

Yes, Gemini can generate Hardware Description Language (HDL) code for FPGA implementation. Currently, there is a huge demand for FPGA developers so the ability to design systems for FPGA implementation is a practical as well as incredibly useful skill.

I designed, implemented, and verified a Universal Asynchronous Receiver/Transmitter (UART) module for FPGAs using SystemVerilog.  The UART was verified in Vivado’s simulation environment.  The design was taken from design entry all the way to bitfile generation for a Digilent Arty S7-50 FPGA development board.

Tools:

AMD (Xilinx) Vivado 2024.2

Gemini

• AI Collaboration: My workflow involved using Gemini to translate high-level requirements into a functional design. The AI generated the initial SystemVerilog code for the receiver/transmitter state machines and the baud rate generator.  Subsequently, it created a comprehensive testbench to verify the module's functionality, drastically reducing the time required for verification.