DigiTekXplorer - UART Design

This is a complete, well-commented SystemVerilog implementation of a UART for an FPGA, featuring a programmable baud rate. 

This design is broken into six logical modules for clarity and reusability:

1. uart_tx.sv (Transmitter): A state machine that takes parallel data and serializes it out according to the UART protocol (Start, Data, Stop bits).
2. uart_rx.sv (Receiver): A more complex state machine that listens for a start bit, oversamples the incoming serial line to reliably capture data, and converts it back to parallel.
3. uart_mn.sv (Main for instantiation): This module instantiates the transmitter and receiver. Crucially, it contains the baud rate generator which creates the timing "ticks" needed by both sub-modules. You program the baud rate by feeding a divider value to this top-level module.
4. uart_top.sv (top-level wrapper): The top-level module makes the design suitable for synthesis and connecting to physical pins.
5. uart_tb.sv (Testbench): serves as a simulation environment to verify the functionality and correctness of the UART design.
6. uart_constraints.xdc (FPGA constraints file): Maps the wrapper's ports to the FPGA pins.