The abCore16 project is a complete, vertically integrated 16-bit computer system designed and written entirely in Python. It constitutes a full software and hardware ecosystem, featuring a custom-designed CPU architecture, a C-like high-level programming language, and a robust toolchain to support the entire development lifecycle.
The abCore16 toolchain is a set of Python-based software tools responsible for taking the programs you write in a high-level C-Like language (SSL) and transforming them into a binary format that our 16-bit abCore16 Microprocessor Simulator can understand and execute. The toolchain consists of four main components: the C-Like Compiler, the SAL Assembler, Simulator, and the Machine Code Disassembler.
The Workflow:
C-like Code (.ssl) -> Compiler -> Assembly Code (.sal) -> Assembler-> Machine Code (.bin) -> Simulator (simulator output to tool terminal)
The C-like High-Level Language (SSL)
This is the primary language for application development. It is designed to be familiar to C programmers but tailored for the abCore16 architecture.
The PLY-Based Compiler
This is the most complex component of the toolchain, responsible for translating the C-like SSL into SAL.
Once SSL is compiled into SAL, the Simple Assembler converts this textual SAL code into the binary machine code for the 16-bit abCore16.
Assembly Listing File (e.g., myProg.asm): Shows SAL alongside calculated 16-bit byte offsets and the symbol table (with 16-bit offsets
The Simple Disassembler provides a way to translate the binary machine code back into a human-readable SAL format, aiding in verification and understanding.
Output: A multi-line string of disassembled SAL code, written to a _disassembled.sal file.
The Simulator acts as the virtual hardware for our system. It loads and runs the binary files produced by the Assembler.
Simulated Components:
The Execution Cycle:
The simulator runs in a main loop that endlessly performs the classic Fetch-Decode-
Execute cycle:
I/O Simulation:
Input and Output are handled via Memory-Mapped I/O (MMIO). Specific memory addresses (0x00FE for input, 0x00FF for output) are treated specially. When the program reads from the input address, the simulator prompts the user for input. When it writes to the output address, the simulator prints the value to the console.
This section demonstrates the execution of a file called test_array.ssl and the abCore16's toolchain output as it progresses from compilation to simulation.
Test Program
The file test_array.ssl is a short test program written in the C-Like language. The file test_array.ssl is shown below:
// test_arrays.ssl
// A program to test the new global array functionality.
// Declare a global array of 5 words and a global variable for indexing.
var my_array[5];
var i;
func main() {
// --- Test 1: Direct write and read with constant indices ---
print 1000; // Marker for start of test 1
my_array[0] = 50;
my_array[1] = 60;
my_array[4] = 90; // Test writing to the last element
print my_array[0]; // Expected output: 50
print my_array[1]; // Expected output: 60
print my_array[4]; // Expected output: 90
// --- Test 2: Using a variable as an index ---
print 2000; // Marker for start of test 2
i = 2;
my_array[i] = 77; // Write to my_array[2]
print my_array[2]; // Expected output: 77
// --- Test 3: Overwriting a value and reading it back ---
print 3000; // Marker for start of test 3
my_array[0] = 55; // Overwrite the first element
i = 0;
print my_array[i]; // Expected output: 55
}
Program Execution
In the PyCharm Terminal I entered:
python main.py test_array.ssl
Terminal Output
After executing the command above, the abCore16 toolchain generated the following output in PyCharm's Terminal:
Found source file: test_arrays.ssl
============================================
STARTING C-LIKE SSL (.ssl) TOOLCHAIN FOR: C-like SSL File 'test_arrays.ssl'
============================================
--- COMPILER (PLY-based via c_ply_compiler.py): Compiling C-like SSL ---
--- COMPILER (PLY-based): Generated SAL successfully ---
PLY COMPILER: Generated SAL saved to 'test_arrays_from_ply.sal'
(Appended HALT to PLY-generated SAL for assembler)
============================================
STARTING TOOLCHAIN FOR PRE-COMPILED: Compiled from C-like SSL File 'test_arrays.ssl' (via PLY)
============================================
--- ASSEMBLER: Assembling SAL Code ---
--- Assembler: Starting First Pass ---
--- Assembler: First Pass Complete ---
Assembler: Assembly listing written to 'test_arrays.asm'
--- Assembler: Starting Second Pass ---
Assembler: Machine code successfully written to 'test_arrays.bin' (219 bytes)
Assembler: Assembly listing written to 'test_arrays.asm'
--- DISASSEMBLER: Disassembling 'test_arrays.bin' ---
DISASSEMBLER: Output successfully written to 'test_arrays_disassembled.sal'
--- SIMULATOR: Loading and Running Binary File ---
SIM MMIO OUTPUT (0x00FFh): 1000
SIM MMIO OUTPUT (0x00FFh): 50
SIM MMIO OUTPUT (0x00FFh): 60
SIM MMIO OUTPUT (0x00FFh): 90
SIM MMIO OUTPUT (0x00FFh): 2000
SIM MMIO OUTPUT (0x00FFh): 77
SIM MMIO OUTPUT (0x00FFh): 3000
SIM MMIO OUTPUT (0x00FFh): 55
--- SIMULATOR: Simulation Log ---
--- Sim Start (DataMemWords:8192, StackBase:2000h, StackLimit:1F00h) ---
MMIO In: 00FEh, MMIO Out: 00FFh
Sim: Binary 'test_arrays.bin' loaded (219B).
PC=0000h SP=2000h Flags:[ZF=0 SF=0 CF=0 OF=0] | Op:0x70(CALL) | Regs:[R0:0000, R1:0000, R2:0000, R3:0000, R4:0000, R5:0000, R6:0000, R7:0000]
CALL: Pushed RetAddr(0x0003h) to Stack[SP=0x1FFFh]. JMP to 0x0004h.
PC=0004h SP=1FFFh Flags:[ZF=0 SF=0 CF=0 OF=0] | Op:0x60(PUSH) | Regs:[R0:0000, R1:0000, R2:0000, R3:0000, R4:0000, R5:0000, R6:0000, R7:0000]
PUSH: R5(0x0000) to Mem[SP=0x1FFEh].
.
.
.
PC=00D9h SP=1FFFh Flags:[ZF=1 SF=0 CF=0 OF=0] | Op:0x71(RET) | Regs:[R0:0000, R1:0000, R2:0000, R3:0000, R4:0000, R5:0000, R6:1000, R7:0037]
RET: Popped RetAddr(0x0003h) from Stack[SP(old)=0x1FFFh]. JMP.
PC=0003h SP=2000h Flags:[ZF=1 SF=0 CF=0 OF=0] | Op:0xFF(HALT) | Regs:[R0:0000, R1:0000, R2:0000, R3:0000, R4:0000, R5:0000, R6:1000, R7:0037]
HALT: CPU Halted by instruction.
--- Sim Finished (CPU HALTED cleanly) (67 cycles) ---
Final PC: 0x0004h
Final Regs: [R0:0x0000, R1:0x0000, R2:0x0000, R3:0x0000, R4:0x0000, R5:0x0000, R6:0x1000, R7:0x0037]
Final SP: 0x2000h
Final Flags: ZF=1 SF=0 CF=0 OF=0
--- SIMULATOR: Final Simulator Register States ---
--- Final Simulator State (print_final_state) ---
Reg R0 : 0 (0x0000) (0000000000000000b)
Reg R1 : 0 (0x0000) (0000000000000000b)
Reg R2 : 0 (0x0000) (0000000000000000b)
Reg R5 : 0 (0x0000) (0000000000000000b)
Reg R6 : 4096 (0x1000) (0001000000000000b)
Reg R7 : 55 (0x0037) (0000000000110111b)
SP: 0x2000h (8192) PC:0x0004h (4) Flags: Z1S0C0O0
Halted: True, Clean Halt: True
Data Mem Sample (size 8192):
(All sampled mem is zero or stack empty at base)
-------------------------------------------
============================================
TOOLCHAIN COMPLETE FOR: Compiled from C-like SSL File 'test_arrays.ssl' (via PLY)
============================================
Successfully processed 'test_arrays.ssl'.
Here is a detailed breakdown of all the files generated by the complete abCore16 toolchain, along with the function that creates each one and its specific purpose in the ecosystem. The toolchain is designed to produce a coordinated set of files that support software simulation, hardware implementation on an FPGA, and detailed debugging at every stage.
1. Primary Build Artifact
This is the core output of the compilation and assembly process.
2. FPGA/Hardware Implementation Files
These files are generated from the .bin file and are specifically for use with Xilinx Vivado and an FPGA.
3. Simulation and Verification Files
These files are generated during the software simulation phase to help verify program correctness and debug its execution.
4. Intermediate and Debugging Files
These files are generated as part of the toolchain process and are primarily used for debugging the tools themselves.
We use cookies to analyze website traffic and optimize your website experience. By accepting our use of cookies, your data will be aggregated with all other user data.