DigiTekXplorer - abCore16 FPGA Implementation

While the primary implementation of the abCore16 toolchain is in Python for simulation and educational purposes, the project also includes conceptual SystemVerilog (a Hardware Description Language, HDL) modules. These modules serve as a blueprint for potentially implementing our custom 16-bit abCore16 microprocessor in actual hardware, typically on an FPGA (Field-Programmable Gate Array).  

The Python-based Microprocessor Simulator provides a cycle-accurate behavioral model of the abCore16. The SystemVerilog design aims to describe this same 16-bit architecture in HDL. This HDL description can then be:

1. Simulated: Using HDL simulators (Vivado Simulator, ModelSim, etc.) to verify the 16-bit hardware logic.
2. Synthesized: Translated by FPGA tools (Xilinx Vivado, Intel Quartus) into a      configuration for an FPGA, realizing the 16-bit CPU.
3. Implemented on an FPGA: Allowing your abCore16 to run compiled and assembled programs on physical hardware, processing 16-bit data and utilizing its 16-bit address space.

The SystemVerilog design for abCore16 is structured modularly:

1. defines.svh (Definitions Header):
   • Contains crucial constant definitions for the 16-bit hardware:
     • Opcodes: Numerical values for machine code instructions (same as the assembler).
     • Register Codes: Numerical codes for the 16-bit registers R0-R7.
     • ALU Control Codes: Defines for selecting 16-bit ALU operations.
     • PC Source Selectors: For controlling the 16-bit Program Counter updates.
     • Memory Parameters: Example definitions for 16-bit wide data memory depth and stack size.

1. alu.sv (16-bit Arithmetic Logic Unit):
   • Implements the core computational logic for 16-bit operands.
   • Takes two 16-bit inputs (R0 and R1) and an ALUControl signal.
   • Outputs a 16-bit result and status flags (Zero, Sign, Carry, Overflow) based on the 16-bit operation performed.

1. datapath.sv (16-bit Datapath Unit):
   • Contains the main hardware components for 16-bit data:
     • Program Counter (PC): A 16-bit register.
     • Instruction Register (IR) components: Registers to hold the multi-byte instruction (opcode and potentially 16-bit immediates/addresses) as it's fetched.
     • Register File: Stores six 16-bit general-purpose registers (R0-R7).
     • Stack Pointer (SP): A 16-bit register, addressing words in the 16-bit wide        data memory.
     • ALU Instance: Instantiates the 16-bit alu.sv module.
     • Multiplexers (MUXes): For selecting 16-bit data sources.
   • Handles 16-bit data movement and operations.

1. control_unit.sv (ControlUnit for 16-bit ISA):
   • The "brain," implemented as a Finite State Machine (FSM) designed for the abCore16's potentially multi-byte instructions (due to 16-bit immediates       and addresses).
   • States: Manages instruction processing: S_FETCH_OPCODE, S_FETCH_OPERAND1 (for 8-bit operand or low byte of 16-bit operand), S_FETCH_OPERAND2 (for high byte of 16-bit operand), S_DECODE, S_EXECUTE, S_MEM_ACCESS, S_WRITEBACK, S_HALTED.
   • Instruction Decoding: Decodes the fetched opcode (from the datapath's IR).
   • Control Signal Generation: Generates signals for the 16-bit datapath, including       those for handling 16-bit immediate values and addresses.
   • Determines the length (1, 2, 3, or 4 bytes) of the current instruction for proper PC       incrementing by the datapath.

1. simple_cpu_top.sv (Top-Level Module for abCore16):
   • Integrates the 16-bit datapath and control_unit.
   • Provides external interfaces for:
     • 16-bit address bus for Instruction Memory (imem_addr_o).
     • 8-bit data bus for Instruction Memory (imem_rdata_i - assuming byte-fetched instructions).
     • 16-bit address bus for Data Memory (dmem_addr_o).
     • 16-bit data bus for Data Memory (dmem_wdata_o, dmem_rdata_i).
     • GPIO (still conceptually 8-bit for simplicity, but could be expanded).